1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly, to an improved semiconductor structure for a ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells and a method of fabricating the same. It is a characteristic feature of the invention that an insulating layer is used for mask programming of data into the ROM device.
2. Description of Related Art
Read-only memory (ROM) is a nonvolatile semiconductor memory widely used in computer and microprocessor systems for permanently storing information including programs and data that are repeatedly used, such as the BIOS (abbreviation for Basic Input/Output System, a widely used operating system on personal computers) or the like. The manufacture of ROMs involves very complicated and time-consuming processes and requires costly equipment and material to achieve. Therefore, the data to be permanently stored in ROMs is usually first defined by the customer and then furnished to the factory to be programmed into the ROMs.
Most ROMs are identical in semiconductor structure except for the different data stored therein. Therefore, the ROM devices can be fabricated up to the stage ready for programming and then the semi-finished products can be stocked in inventory to await customer orders. The customer then furnishes the data to the factory where the data are to be stored in the semi-finished ROMs by using the so-called mask programming process. This procedure is now a standard method in the semiconductor industry for fabricating ROMs.
In most ROMs, metal-oxide semiconductor field-effect transistors (MOSFET) are used as the memory cells for stored data. In the mask programming stage, impurities are selectively diffused into specific channels of the MOSFET memory cells so as to change the threshold voltage thereof, thereby setting the MOSFET memory cells to ON/OFF states representing different binary data. The MOSFET memory cells are connected to the external circuits via a plurality of polysilicon-based word lines and bit lines. The channel regions are located beneath the word lines and between each pair of adjacent bit lines. Whether one MOSFET memory cell is set to store a binary digit of 0 or 1 is dependent on whether the associated channel is diffused with impurities or not. If the associated channel is diffused with impurities, the MOSFET memory cell is set to have a low threshold voltage, effectively setting the MOSFET memory cell to a permanently-ON state representing the storage of a binary digit of 0, for example; otherwise, the MOSFET memory cell is set to have a high threshold voltage, effectively setting the MOSFET memory cell to a permanently-OFF state representing the storage of a binary digit of 1.
One conventional ROM device is shown in FIGS. 1A through 1C, in which FIG. 1A is a schematic top view of the ROM device; FIG. 1B is a cross-sectional view of the ROM device of FIG. 1 cutting through the line 1B--1B ; and FIG. 1C is a cross-sectional view of the ROM device of FIG. 1 cutting through the line 1C--1C.
As shown, the conventional ROM device includes a semiconductor substrate, such as a P-type silicon substrate, on which a plurality of parallel-spaced bit lines 11 and a plurality of parallel-spaced word lines 13 intercrossing the bit lines 11 are formed. The word lines 13 are separated from the underlying bit lines by an oxidation layer 12. This ROM device includes a plurality of MOSFET memory cells, each being associated with one segment of the word lines 13 between each neighboring pair of the bit lines 11.
Referring to FIG. 1C, in the method for fabricating the foregoing ROM device, the first step is to conduct an ion implantation process so as to diffuse an N-type impurity material, such as arsenic (As), into selected regions of the substrate 10 to form a plurality of parallel-spaced diffusion regions serving as the bit lines 11 The interval region between each neighboring pair of the bit lines 11 serves as a channel region 16. Subsequently, a thermal oxidation process is performed on the wafer so as to form the oxidation layer 12 over the entire top surface of the wafer. Next, a conductive layer, such as a highly-doped polysilicon layer is formed over the wafer, and then selectively removed through a photolithographic and etching process. The remaining portions of the conductive layer serve as the word lines 13. This completes the fabrication of a semi-finished product of the ROM device awaiting a customer order.
In the mask programming process, a mask 15 is placed over the wafer. This mask 15 is predefined to form a plurality of openings according to the bit pattern of the data that are to be programmed into the ROM device for permanent storage. These openings expose those channel regions that are associated with a selected group of MOSFET memory cells that are to set to a permanently-ON state, with all the other MOSFET memory cells being to be set to a permanently-OFF state. Subsequently, an ion implantation process is conducted on the wafer so as to diffuse a P-type impurity material, such as boron, into the exposed channel regions. This completes the so-called code implant process.
In the finished product of the ROM device, the doped channel regions cause the associated MOSFET memory cells to be set to have a low threshold voltage, effectively setting the MOSFET memory cells to a permanently-ON state representing the permanent storage of a first binary digit, for example 0. On the other hand, the undoped channel regions cause the associated MOSFET memory cells to be set to have a high threshold voltage, effectively setting the MOSFET memory cells to a permanently-OFF state representing the permanent storage of a second binary digit, for example 1.
The threshold voltage level of each MOSFET memory cell is dependent on the concentration of the impurity ions diffused into the associated channel region. If the concentration is too high, the threshold voltage of the associated MOSFET memory cell will be raised to a higher level. This may cause the undesired effect of junction breakdown between the source/drain regions and the substrate. To prevent the junction breakdown, the concentration of the implanted impurity ions should be reduced. However, this will cause a decrease in the ratio of the ON-current I.sub.ON to the OFF-current I.sub.OFF (I.sub.ON refers to the current flowing through a permanently-ON MOSFET memory cell during access operation, while I.sub.OFF refers to the current flowing through a permanently-OFF MOSFET memory cell during access operation). This drawback will cause the external circuitry to have difficulty in distinguishing between the ON/OFF states of the MOSFET memory cells of the ROM device during access operation. Moreover, the existence of a diode junction between the source/drain regions during access operation causes a large leakage current in the ROM device.